With the advent of 4G times, wireless communication networks such as 2G, 3G, Wireless Fidelity (WiFi) and the like would not disappear immediately or exit a market; instead, they would coexist for a very long time. The vigorous development of the wireless communication technology triggers the tendency of network heterogeneity; and various wireless technologies emerge in endlessly to provide extensive and heterogeneous network environments for users, including a wireless personal area network such as Zigbee and Bluetooth, a wireless local area network such as WiFi, a wireless metropolitan area network such as 802.16 Worldwide Interoperability for Microwave Access (WiMAX), a wireless mobile wide area network such as 2G and 3G, a satellite network, a point-to-point (Ad Hoc) network, a wireless sensor network, and so on. In order to satisfy requirements of a user on roaming and to make full use of various heterogeneous network resources, a terminal technology must develop towards multimode and intelligentization. It is an irreversible tendency for terminals to evolve towards the direction of supporting cognitive radio and reconfigurable dynamic spectrum access in future.
A Software Defined Radio (SDR) technology is the most optimum approach to realize the support for the cognitive radio and dynamic spectrum access with a low cost.
When a vector processor is adopted to serve as basic hardware of the SDR technology to process a base-band physical layer signal, generally a scalar master control processor is needed to serve as hardware to run a high-layer protocol and control process. Since the master and slave processors need to pass a lot of parameters when implementing multimode, a conventional method, as shown in FIG. 1, is to pass all the parameters through a Mailbox mechanism formed by port registers or a dual-port Random Access Memory (RAM) at the periphery of the processor; in this way, a large number of port registers is consumed, and a chip area and power consumption of the processor are increased. Moreover, when the vector processor acquires a parameter, a cycle delay is needed in accessing the peripheral port; and thus parameter transmission efficiency is reduced.